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1 wideband, low noise, low distortion, fixed gain, differential amplifier ISL55211 the ISL55211 is a wideband, differential input to differential output amplifier offering 3 possible internal gain settings. using fixed 500 ? internal feedback resistors, the amplifier may be configured for a differential gain of 2, 4 or 5v/v depending on which combination of input pins are connected to the signal source. internal feedback capacitors controls the signal bandwidth to be a constant 1.4ghz in all gain settings. ideally suited for ac-coupled da ta acquisition applications, the output dc common mode voltage is controlled through an external v cm pin or left to default to 1.2v above the negative supply pin. where the differential signal source is ac-coupled, the input common mode voltage will equal the output common mode voltage. intended for very high dynamic range adc interface applications, the ISL55211 offers 5600v/s differential slew rate, <12nv/ hz output noise, and >100dbc sfdr to >100mhz for 2v p-p 2-tone 3rd order intermodulation. its balanced architecture effect ively suppresses even order distortion terms - an important issue for very wide band 1st nyquist zone adc interface applications. minimum gain operation of 2v/v (6db) with <1db peaking ensures stable performance over-temperature. it's ultra high differential slew rate of 5600v/s provides adequate performance margin for large signal application through 500mhz. the ISL55211 requires only a single 3.3v (max. 4.2v) power supply and 35ma quiescent current, providing a very low power solution (115mw). furt her power savings are possible using the optional power shutdown control - where the quiescent current can be reduced to <0.4ma. a companion device, the isl55210, offers similar performance where the feedback and gain resistors are external. both are available in a 16 ld tqfn (pb-free) pa ckage and are specified for operation over the -40c to +85c ambient temperature range. features ? 3 fixed gain options . . . . . . . . . . . . . . . . . . . . . . . 2, 4, or 5v/v ? constant bandwidth over gain . . . . . . . . . . . . . . . . . . 1.4ghz ? differential slew rate . . . . . . . . . . . . . . . . . . . . . . . 5,600v/s ?2v p-p , 2-tone im3 (200 ? ) 100mhz . . . . . . . . . . . . . . -103dbc ? low differential output noise (gain 5v/v) . . . . . . <12nv/ hz ? supply voltage range . . . . . . . . . . . . . . . . . . . . . . 3.0v to 4.2v ? quiescent power (3.3v supply) . . . . . . . . . . . . . . . . . .115mw applications ? low power, high dynamic range adc interface ? differential mixer output amplifier ? saw filter pre/post driver ? fixed gain coax receiver related devices ? isl55210 - external gain set version ? isla112p50 - 12-bit, 500msps adc (<500mw) ? isla214p50 - 14-bit, 500msps adc (<850mw) related literature ? an1649 - ?designer?s guide to the isl55210 and ISL55211 evaluation boards? -13 -10 -7 -4 -1 2 5 8 11 14 17 20 23 1m 10m 100m 1g 50 1:2 ISL55211 +3.3v + - v cm 22pf 10 300 8pf isla214p50 1:1.4 50 v cm adt4-1t adt2-1t v i g = 5v/ v 120nh 120nh v adc high gain, very low power, adc interface with 3 rd order output filter 20 log v adc v i = 20db 35ma (115mw) 14bit 500msps 180mv p-p for adc -1dbfs 1.2v (850mw) 10 50 figure 1. typical application circuit frequency (hz) gain (db) measured frequency response june 21, 2011 fn7868.0 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2011. all rights reserved intersil (and design) and femtocharge are trademarks owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
ISL55211 2 fn7868.0 june 21, 2011 pin configuration ISL55211 (3x3 16 ld tqfn) top view gnd nc nc gnd gnd v cm v s+ v o- v o+ v s+ 1 2 3 4 56 78 9 10 11 12 13 14 15 16 + - v cm v in1+ v in2+ gnd gnd 500 pd v in2- v in1- 0.2pf 0.2pf 750 750 500 140 348 348 140 pin descriptions pin number symbol description 1v in2- balanced differential input for av = 6db, strapped to v in1- for av = 14db 2v in1- balanced differential input for av = 12db, strapped to v in2- for av = 14db 3v in1+ balanced differential input for av = 12db, strapped to v in2+ for av = 14db 4v in2+ balanced differential input for av = 6db, strapped to v in1+ for av = 14db 5, 8, 13, 16 gnd supply ground (the rmal pad electrically connected) 6, 15 v s+ positive power supply (3.0v~4.2v) 7 pd power-down: pd = logic low. puts part into low power mode; pd = logic high or open for normal operation 9v o- inverting amplifier output 10, 11 nc no internal connection 12 v o+ non-inverting amplifier output 14 v cm common-mode voltage input ordering information part number (notes 1, 2, 3) part marking temp range (c) package (pb-free) pkg. dwg. # ISL55211irtz 5211 -40 to +85 16 ld 3x3 tqfn l16.3x3d ISL55211irtz-eval1z evaluation board notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for ISL55211 . for more information on msl please see techbrief tb363 .
ISL55211 3 fn7868.0 june 21, 2011 absolute maximum ratings (t a = +25c) thermal information supply voltage from v s+ to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5v input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .v s+ +0.3v to gnd-0.3v power dissipation. . . . . . . . . . . . . . . . . . . . see thermal conditions section esd rating esd rating human body model (per mil-std-883 method 3015.7) . . . . . . . . 3500v machine model (per eiaj ed-4701 method c-111) . . . . . . . . . . . . . 250v charged device model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500v latch up (per jesd-78; class ii; level a) . . . . . . . . . . . . . . . . . . . . . . 100ma thermal resistance (typical) ja (c/w) jc (c/w) 16 ld tqfn package (notes 4, 5) . . . . . . . 63 16.5 storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65c to +125c max. continuous operating junction temperature . . . . . . . . . . . . .+135c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions ambient operating temperature . . . . . . . . . . . . . . . . . . . . . -40c to +85c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications v s+ = +3.3v test conditions: g = 12db, v cm = open, v o = 2v p-p , r l = 200 differential, t a = +25c, differential input, differential output, input and output referenced to internal default v cm (1.2v nominal) unless otherwise specified. parameter conditions min (note 6) typ max (note 6) unit tested ac performance small-signal bandwidth (4-port s parameter, test circuit 2) g = 6db, v o = 100mv p-p 1.6 ghz g = 12db, v o = 100mv p-p 1.4 ghz g = 14db, v o = 100mv p-p 1.4 ghz bandwidth for 0.1-db flatness g = 12db, v o = 2v p-p (figure 17) 150 mhz large-signal bandwidth g = 12db, v o = 2v p-p 1.2 ghz gain accuracy g = 6db, r l = open 1.96 2 2.04 v/v * g = 12db, r l = open 3.88 4 4.12 v/v * g = 14db, r l = open 4.8 5 5.2 v/v slew rate (differential) 5,600 v/s differential rise/fall time 2-v step (simulated) 0.22 ns 2nd-order harmonic distortion, test circuit 1, 15db gain f = 20mhz, v o = 2v p-p -110 dbc f = 50mhz, v o = 2v p-p -98 dbc f = 100mhz, v o = 2v p-p -85 dbc 3rd-order harmonic distortion, test circuit 1, 15db gain f = 20mhz, v o = 2v p-p -120 dbc f = 50mhz, v o = 2v p-p -110 dbc f = 100mhz, v o = 2v p-p -100 dbc 2nd-order intermodulation distortion, test circuit 1, 15db gain f c = 70mhz, 200khz spacing (2v p-p envelope) -89 dbc f c = 140mhz, 200khz spacing (2v p-p envelope) -78 dbc 3rd-order intermodulation distortion, test circuit 1, 15db gain f c = 70mhz, 200khz spacing (2v p-p envelope) -104 dbc f c = 140mhz, 200khz spacing (2v p-p envelope) -92 dbc output voltage noise test circuit 1, total gain 15db, adt2-1t 11.2 nv/ hz dc performance (internal nodes) input offset voltage t a = +25c -1.4 0.1 +1.4 mv * t a = -40c to +85c -1.6 0.1 +1.6 mv
ISL55211 4 fn7868.0 june 21, 2011 average offset voltage drift t a = -40c to +85c 3 v/ c input bias current t a = +25c, positive current into the pin +50 +120 a * t a = -40c to +85c +50 +140 a average bias current drift t a = -40c to +85c 200 na/ c input offset current t a = +25c -5 1 +5 a * t a = -40c to +85c -6 +6 a average offset current drift t a = -40c to +85c 8 na/ c input common-mode input range high internal nodes 1.7 v * common-mode input range low internal nodes 1.1 v * common-mode rejection ratio f < 10mh z, common mode to differential output 56 75 db * differential input impedance v in1- connected to v in2- v in1+ connected to v in2+ 200 output (pins 9 and 12) maximum output voltage each output (with 200 differential load) linear operation 2.15 2.35 v * minimum output voltage 0.45 0.63 v * differential output voltage swing t a = +25c 3.04 3.8 v p-p * t a = -40c to +85c 2.95 v differential output current drive r l = 10 [sourcing or sinking] 40 45 ma * closed-loop output impedance f < 10mhz, differential 0.6 output common-mode voltage control (pin 14) small-signal bandwidth from v cm pin to output v cm 30 mhz slew rate rising/falling 150 v/s gain v cm input pin 1.0v to 1.4v 0.995 0.999 v/v * output common-mode offset from cm input -8 1 +8 mv * cm default voltage output v cm with v cm pin floating 1.18 1.2 1.22 v * cm input bias current at control pin 2 a cm input voltage range at control pin 0.9 1.9 v * cm input impedance at control pin 15 || 50 k || pf power supply specified operation voltage 3 3.3 4.2 v * quiescent current t a = +25, v s+ = 3.3v, v s- = 0v 33 35 37 ma * t a = -40c to +85c 30.5 35 39.5 ma power-supply rejection (psrr) v s+ 3.0v to 4.5v range f < 10mhz [psrr to differential output] 50 67 db * power-down (pin 7) referenced to gnd enable voltage threshold assured on above 1.55v 1.3 1.55 v * disable voltage threshold assured off below 0.54v 0.54 0.7 v * electrical specifications v s+ = +3.3v test conditions: g = 12db, v cm = open, v o = 2v p-p , r l = 200 differential, t a = +25c, differential input, differential output, input and output referenced to internal default v cm (1.2v nominal) unless otherwise specified. (continued) parameter conditions min (note 6) typ max (note 6) unit tested
ISL55211 5 fn7868.0 june 21, 2011 power-down quiescent current t a = +25c 0.2 0.3 0.4 ma * t a = -40c to +85c 0.15 0.45 ma input bias current pd = 0v, current positive into pin -5 1 +5 a input impedance 2 || 5m || pf turn-on time delay measured to output on 200 ns turn-off time delay measured to output off 400 ns note: 6. compliance to datasheet limits is assu red by one or more methods: production test, characterization, and/or design. electrical specifications v s+ = +3.3v test conditions: g = 12db, v cm = open, v o = 2v p-p , r l = 200 differential, t a = +25c, differential input, differential output, input and output referenced to internal default v cm (1.2v nominal) unless otherwise specified. (continued) parameter conditions min (note 6) typ max (note 6) unit tested figure 2. intended configuration + - 500 500 r g r g 1:n 50 input ISL55211 v i v o r t table 1. ISL55211 intended transformer + internal gain settings input xfmr turns ratio internal r g value ( ) gain (v/v) v o /v i gain (db) v o /v i r t value ( ) to get 50 match 1:1.4 250 2.8 9 122 1:1.4 125 5.6 15 162 1:1.4 100 7 17 192 1:2 250 4 12 333 1:2 125 8 18 1020 1:2 100 10 20 open
ISL55211 6 fn7868.0 june 21, 2011 typical performance curves v s+ = 3.3v, t a +25c, unless otherwise noted. figure 3. small signal freque ncy response with adt2-1t input transformer figure 4. small signal fr equency response with adt4-1wt input transformer figure 5. large signal freque ncy response with adt2-1t input transformer figure 6. large signal fr equency response with adt4-1wt input transformer figure 7. noise figure with adt2-1t input transformer f igure 8. noise figure with adt4-1wt input transformer -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 10m 100m 1g frequency (hz) av = 2 av = 4 av = 5 test circuit #1 v o = 500mv p-p normalized gain (db) -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 10m 100m 1g frequency (hz) av = 2 av = 4 av = 5 test circuit #1 v o = 500mv p-p normalized gain (db) -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 10m 100m 1g frequency (hz) av = 2 av = 4 av = 5 test circuit #1 v o(p-p) = 3v p-p normalized gain (db) -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 10m 100m 1g frequency (hz) av = 2 av = 4 av = 5 test circuit #1 v o(p-p) = 3v p-p normalized gain (db) 0 5 10 15 20 25 50 100 150 200 250 300 350 400 450 500 frequency (mhz) noise figure (db) gain = 9db gain = 17db gain = 15db test circuit #1 0 2 4 6 8 10 12 14 16 18 20 50 100 150 200 250 300 350 400 450 500 frequency (mhz) noise figure (db) gain = 12db gain = 20db gain = 18db test circuit #1
ISL55211 7 fn7868.0 june 21, 2011 figure 9. hd2, hd3 vs output swing figure 10. im2 and im3 vs output swing figure 11. hd2, hd3 vs gain figure 12. im2 and im3 vs gain figure 13. hd2, hd3 vs differential load figure 14. im2, im3 vs differential load typical performance curves v s+ = 3.3v, t a +25c, unless otherwise noted. (continued) -110 -105 -100 -95 -90 -85 -80 -75 -70 -65 -60 50m 100m 150m 200m test circuit 1 r l = 200 gain = 15db frequency (hz) hd2, hd3 spurious (dbc) hd3 of 2v p-p hd3 of 1v p-p hd2 of 1v p-p hd3 of 3v p-p hd2 of 3v p-p hd2 of 2v p-p -120 -110 -100 -90 -80 -70 -60 50 100 150 200 frequency (mhz) im2, im3 spurious (dbc) test circuit 1 r l = 200 gain = 15db im3 of 2v p-p im2 of 3v p-p im3 of 3v p-p im2 of 2v p-p im2 of 1v p-p im3 of 1v p-p -110 -105 -100 -95 -90 -85 -80 -75 -70 -65 -60 50m 100m 150m 200m frequency (hz) hd2, hd3 spurious (dbc) test circuit 1 r l = 200 v o = 2v p-p hd3 of 15db hd3 of 9db hd3 of 17db hd2 of 17db hd2 of 9db hd2 of 15db -120 -110 -100 -90 -80 -70 -60 50m 100m 150m 200m frequency (mhz) test circuit 1 v o = 1v p-p each tone im3 of 15db im2 of 15db im2 of 17db im3 of 17db im2 of 9db im3 of 9db im2, im3 spurious (dbc) -110 -100 -90 -80 -70 -60 -50 50m 100m 150m 200m frequency (hz) test circuit 1 gain = 15db hd2 of 100 hd2 of 50 hd2 of 200 hd2 of 500 hd3 of 500 hd3 of 200 hd3 of 50 hd3 of 100 hd2, hd3 spurious (dbc) -130 -120 -110 -100 -90 -80 -70 -60 -50 50m 100m 150m 200m frequency (hz) test circuit 1 im3 of 50 im2 of 100 im3 of 100 im3 of 500 im2 of 500 im3 of 200 im2 of 200 im2 of 50 im2, im3 spurious (dbc)
ISL55211 8 fn7868.0 june 21, 2011 figure 15. phase and group delay vs gain figure 16. differential output noise vs gain figure 17. small signal frequency response figure 18. differential output impedance figure 19. v cm pin input frequency response to output common mode figure 20. output balance error typical performance curves v s+ = 3.3v, t a +25c, unless otherwise noted. (continued) 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 80 100 120 140 160 180 200 10 30 50 70 90 110 130 150 170 190 frequency (mhz) phase () group delay (ns) group delay of 17db phase of 17db group delay of 15db group delay of 9db phase of 15db phase of 9db test circuit 1 with adt2-1t input 5 6 7 8 9 10 11 12 13 14 15 1m 10m 100m frequency (hz) gain = 17db gain = 15db gain = 9db test circuit 1 adt2-1t output noise including 50 source noise output spot noise (nv/ hz) -12 -9 -6 -3 0 3 10 100 1000 frequency (mhz) normalized gain (db) 6db 14db 12db test circuit 2 no transformers 5000 0 2 4 6 8 10 12 1m 10m 100m 1000m frequency (hz) output impedance ( ) gain = 2 gain = 5 gain = 4 test circuit 2 simulated -21 -18 -15 -12 -9 -6 -3 0 3 110 frequency (mhz) 200mv p-p 10mv p-p gain (db) 100 200 test circuit 3 common mode ac output -80 -75 -70 -65 -60 -55 -50 2m 20m 200m frequency (hz) differential to common mode conversion (dbc) 17db 15db 9db test circuit 3 v o(p-p) differential is 2v p-p
ISL55211 9 fn7868.0 june 21, 2011 figure 21. small signal step resp onse figure 22. large signal response figure 23. enable/disable times (2s/div) figure 24. shutdown feed-through figure 25. overdrive recovery figure 26. psrr/cmrr to differential v o typical performance curves v s+ = 3.3v, t a +25c, unless otherwise noted. (continued) -0.15 -0.10 -0.05 0 0.05 0.10 0.15 0 2 4 6 8 10 12 14 16 18 20 timebase (ns) amplitude (v) output input test circuit #1 with adt2-1t 100mhz square wave input -1.5 -1 -0.5 0 0.5 1.0 1.5 02468101214161820 timebase (ns) amplitude (v) output input test circuit #1 with adt2-1t 100mhz square wave input pd 100mhz output disabled enabled 2s/div 100mhz output disabled enabled 2s/div test circuit 1 -16.0 -15.8 -15.6 -15.4 -15.2 -15.0 -14.8 -14.6 -14.4 1m 10m 100m frequency (hz) output vs input (dbc) 100mv p-p 2v p-p test circuit 1 with adt2-1t input output v p-p relative to input v p-p -2.5 -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 2.5 0 20 40 60 80 100 120 140 160 180 200 time (ns) input and output waveforms (v) output input test circuit 1 1 10 100 1000 frequency (mhz) psrr/cmrr (db) 35 45 55 65 75 85 95 psrr to v o (differential) cmrr to v o (differential) test circuit 1 simulated exact external r?s
ISL55211 10 fn7868.0 june 21, 2011 applications basic operation the ISL55211 is a very wideband, voltage feedback based, differential amplifier including an output common mode control loop and optional power shutdown feature. intended for very low distortion differential signal driving, this internally fixed gain device provides 3 possible gain settings by simply picking the input side connections as shown in table 1. including internal compensation, the is l55211 holds a constant bandwidth over gain settings. most applications are intended for ac-coupled i/o using a single 3.3v supply and an input transformer. the internal resistor values have been scaled up slightly to require an external termination element along with the two internal resistors where a 50 ? differential input match is de sired. this does increase the output noise slightly but narrows up the input vswr tolerance and lowers the added loading of the feedback resistors improving sfdr. where dc-coupled differential i/o operation is desired, the ISL55211 can be connected directly to the source as long as the internal input common mode range limits are observed (1.1v to 1.7v for a 3.3v single supply op eration). for a dc-coupled, single to differential requirement, consider the isl55210. this device is an external resistor version of the ISL55211 where the flexibility in the external resistors will enable single to differential operation. for a ground referenced input signal, this will require a negative supply when using the isl55210. most applications behave as a differential inverting op amp design. there is therefore an input gain resistor on each side of the inputs that must be driven. the 3 possible connections to the two pairs of input pins will give a 100 ? , 125 ? , or 250 ? input resistor on each side. combined with the two input turns ratio's shown in table 1, gives a 9db to 20db operating gain range in approximately 3db steps. the device can be powered down to < 400a supply current using the optional disable pin. to operate normally, this pin should be asserted high using a simple logic gate to +v cc or tied high through a 10k ? resistor to +v cc . when disabled, the power dissipation drops to < 1mw but, due to the inverting op amp type architecture, the input signal will feed-forward through the feedback and gain resistors giving limited isolation. application and characterization circuits test circuit 1 of figure 29 forms a starting point for many of the characterization curves for the ISL55211. since most lab sources and measurement devices are single -ended, this circuit converts to differential at the input through a wideband transformer and would also be a typical application circuit coming from a single-ended sour ce. assuming the source is a 50 ? impedance, the internal r g resistors and external r t are set to provide both the input termination and the ga in. since the inverting summing nodes act as virtual ground points for ac signal analysis, the total termination impedance across th e input transformer secondary will be (2*r g )||r t . setting this equal to n 2 *r s will give a matched input impedance inside the bandwidth of the transformer (where "n" is the turns ratio). the amplifier gain is fixed by the selected input r g element and the internal 500 ? feedback resistors. while the ISL55211 is internally a voltage feedback design (vfa) to give the lowest possible noise, internal compensation caps hold the bandwidth over gain setting approximately constant at 1. 4ghz. for wider small signal bandwidth at lower gains, consider the isl55210, which provides >2.2ghz at a gain of 12db. figure 27. default v cm and max v opp vs supply voltage figure 28. supply current vs supply voltage typical performance curves v s+ = 3.3v, t a +25c, unless otherwise noted. (continued) 1 2 3 4 5 6 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0 4.1 4.2 4.3 4.4 4.5 supply voltage (v) internally set v cm maximum differential v p-p output using default v cm output default v cm and max differential v opp (v) test circuit 1 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0 4.1 4.2 4.3 4.4 4.5 single supply voltage (v) t a = +25c t a = -40c t a = +85c supply current (ma) test circuit 1
ISL55211 11 fn7868.0 june 21, 2011 working with a transformer coupled input as shown in figure 29, or with two dc blocking caps from a differential source, means the output common mode voltage set by either the default internal v cm setting, or a voltage applied to the v cm control pin, will also appear as the input common mode voltage. this provides a very easy way to control the ISL55211 i/o common mode operating voltages for an ac-coupled signal path. the internal common mode loop holds the output pins to v cm and, since there is no dc path for an i cm current back towards the input in figure 29, that v cm setting will also appear as the input common mode voltage. it is useful , for this reason, to leave any input transformer secondary centertap unconnected. the internally set v cm voltage is referenced from the negative supply pin. with a single 3.3v supply, it is very close to 1.2v but will change with total supply voltage across the device as shown in figure 27. most of the characterization curv es starting with figure 29 then get different gains by changing the connections to the two pairs of input r g connections, as shown on the pin configuration drawing on page 2. two input turns ratios are intended for test circuit 1; either a 1:1.4 turns rati o (ohms ratio of 2) or a 1:2 turns ratio (ohm ratio of 4). the specific transformers shown in figure 29 are representative of broadband rf transformers but alternate devices and manufacturers of these turns ratio devices are certainly applicable. the outp ut side of this test circuit presents a differential 200 ? load while converting the differential to single-ended thro ugh a resistive attenuator and a 1:1 transformer. this inserts approximately a 17db insertion loss that is removed to report the char acteristic curves. for load tests below the 200 ? shown in figure 29, a simple added shunt resistor is placed across the output pins. for loads > 200 ? , the series and shunt load r's are adjusted to show that total load (including the 50 ? measurement load reflected through the 1:1 output measurement port transfor mer) and provide an apparent 50 ? differential source to that transformer. this output side transformer is for measurement purposes only and is not necessary for final applications circuits. there are output interface designs that do benefit from a transformer as part of the signal path as shown in figure 1. in that case, the 1:1:4 output side transformer becomes part of a filter design and recovers the filter insertion loss from the amplifier output pins to the adc inputs. where just the amplifier is tested , a 4-port network analyzer is used and the very simple test circuit of figure 30 is implemented. this is used to measure the differential s21 curves vs gain of figure 17 and as a simu lation circuit for the differential output impedance vs gain of figure 18. changing the gain is a simple matter of adjusting the connections to the four input r g connections resistors, as shown in table 1. this circuit depends on the two ac-coupled source 50 of the 4 port network analyzer and presents an ac-coupled differential 100 load to the amplifier as the input impedance of the remaining two ports of the network analyzer. using this measurement allows the small single bandwidth of just the ISL55211 to be exposed. many of the other measurements are using i/o transf ormers that ar e limiting the apparent bandwidth to a reduced level. figure 17 shows the 3 normalized differential s21 curves for the possible internal gains of 9db, 14db and 15db. the smal l signal bandwidth is remaining nearly constant at 1.4ghz due to the internal capacitive feedback network. the closed loop differential outp ut impedance of figure 18 is simulated using figure 30 in ads. this shows a relatively low output impedance (< 1 ? through 100mhz) constant with signal gain setting. typical fda output s show a closed loop output impedance that increases with si gnal gain setting. the ISL55211 holds a more constant response du e to internal design elements unique to this device. common mode output measurements are made using the circuit in figure 31. here, the outputs are summed together through two 100 ? resistors (still a 200 ? differential load) to a center point where the average, or common mode, output voltage may be sensed. this is coupled through a 1f dc blocking capacitor and measured using 50 ? test equipment. the common mode source impedance for this circuit is the parallel combination of the 2-100 ? elements, or 50 ? . figure 19 uses this circuit to measure the small and large signal response from the v cm control pin to the output common mode. this pin includes an internal 50pf capacitor on the default bias network (to filter supply noise when there is no connection to this pin), which bandlimits the response to approximately 30mhz. this is far lower than the actual bandwidth of the common mode l oop. figure 20 uses this output figure 29. test circuit 1 50 1f 1:1.4 1f 1f 85 ISL55211 +3.3v + - v i 35 35 adt2- 1t or adt4- 1wt 0.1f v cm 500 500 35ma 115mw 1:1 adt1- 1wt 50 1f v m v o r g r g pd 0.2pf 0.2pf r t 200 85 10k figure 30. test circuit 2 4-port s-parameter measurements ISL55211 +3.3v + - 50 50 v cm r f r f 50 1/2 of a 4-port s-parameter 1/2 of a 4-port s-parameter 10k pd r g r g r t 50
ISL55211 12 fn7868.0 june 21, 2011 cm measurement circuit with a large signal (2v p-p ) differential output voltage (generated through the vi path of figure 31) to measure the differential to common mode conversion - often called the "output balance error" for an fda. single supply, input transformer coupled, design considerations the characterization circuit of figure 29 shows one possible input stage interface that offers several advantages. where ac coupling is adequate, the circuit of figure 29 simplifies the input common mode voltage control. if the source coming into this stage is single-ended, the inpu t transformer pr ovides a zero power conversion to differential. the two gain resistors (r g in figure 29) provide both a portion of the input termination impedance and the gain element for the amplifier. for 50 ? systems, these r g resistors are too high with the turns ratios shown in figure 29 to provide the full match and an external r t resistor is required. this r t element goes away at the highest gain setting using a 1:2 input turns ratio transformer. it is also possible to adapt this ci rcuit to other input characteristic impedances. figure 32 shows a 75 ? example similar to figure 2 while table 2 shows the necessary external r values and resulting gains. here, the sum of the two internal r g resistors at the higher two gain settings is too low to retain a match for the 1:2 input step up case. there, a pair of external series resistors are added to get the total differential input impedance up to 300 ? on the secondary side of the transformer and the r t element goes to infinity. these two conditions are not particularly useful but figure 32 shows how to implement the full range of internal conditions with the two turns ratios considered in table 2. figure 32 also shows a pair of alternate input transformer types from pulse engineering particularly suitable to the 75 ? case. this input interface also simplifies the input common mode control. the v cm pin controls the output common mode voltage. in most dc-coupled fda applications, the input common mode voltage is determined by both th is output common mode and the source signal. in a configuration like figure 29, there is no path for a common mode current to flow from output to input, so the input common mode voltage equals the output. a similar effect could be achieved with just two blocking caps on the two r g resistors. a dc-coupled, single to differential, configuration will also have a common mode input that is moving with the input signal. converting to just a differen tial signal at the amplifier, as in figure 29, removes any input signal related artifacts from the input common mode making the ISL55211 behave as a differential only vfa amplifier. there is only a very small differential error signal at the inpu ts set by the loop gain, as in a figure 31. test circuit #3 common mode ac output measurements 50 1f 1:1.4 ISL55211 +3.3v + - r g r g v cm 500 500 100 100 adt2-1t 1f v i 10k pd 50 output v cm 50 v cm input 1f table 2. external resistors for a 75 input impedance design ISL55211 intended transformer + internal gain settings input xfmr turns ratio internal r g value ( ) gain (v/v) v o /v i gain (db) v o /v i external r t value ( ) external r s value ( ) 1:1.4 250 2.8 9 214 0 1:1.4 125 5.6 15 375 0 1:1.4 100 7 17 600 0 1:2 250 4 12 750 0 1:2 125 6.7 16.5 open 25 1:2 100 6.7 16.5 open 50 figure 32. 75 impedance implementations + - 500 500 r g r g 1:n 75 input ISL55211 vi v o r t 1:1.4 -> cx2045nl 1:2 -> cx2032 r s r s
ISL55211 13 fn7868.0 june 21, 2011 normal single-ended vfa applic ation, but no common mode signal related terms. the examples shown are using the transformer to convert from single to differential. howeve r, if the source is already differential, these same transfor mer input circuits can drive the transformer differentially still providing impedance scaling if needed and common mode rejection for both dc and ac common mode issues. a good example would be differential mixer outputs or saw filter outp uts. those differential sources could also be connected into the ISL55211 r g resistors through blocking caps as well eliminating the input transformer. the ac termination impedance for the diff erential source will then be the sum of the two r g resistors when simple blocking caps are used. amplifier i/o range limits the ISL55211 is intended principally to give the lowest im3 performance on the lowest power for a differential i/o application. the amplifier will work dc coupled and over a relatively wide supply range of 3.0v to 4.2v supplies. the outputs have both a differential and common mode operating range limits while the input pins internal to the ISL55211 have a common mode voltage operating range. for single supply operation, the -vs pins are at ground as is the exposed metal pad on the underside of the package. the ISL55211 can operate split supply where then -vs will be a negative supply voltage and the exposed metal pad is either connected to this negative supply or left unconnected on an insulating board layer. briefly, the i/o and v cm limits are as follows: 1. maximum v cm setting = -vs +2v 2. input common mode operat ing range (internal summing junction pints of the ISL55211) of -vs + 1.1v or to output v cm + 0.5v 3. output v o minimum (on each side) is either -vs + 0.3v or output v cm - 0.9v 4. output v o maximum (on each side) is +vs - 1.5v the output swing limits are often asymmetrical around the v cm voltage. the maximum single-ended swings are set by these two limits - v o(min) is either -vs + 0.3v or v cm - 0.9v, whichever is less. so for instance, on a single 3.3v supply with the default v cm voltage of 1.2v, these two limits give the same result and the output pins can swing down to 0.3v above -vs (= 0v). if, however, the v cm pin is raised to 1.5v, then the minimum output voltage will become 1.5v - 0.9v = 0.6v. v o(max) is set by a headroom limit to the positive supply to be -v o(max) = +vs - 1.5v. again, on a 3.3v single supply and the default 1.2v v cm setting, this means the maximum referenced to ground output pin voltages can be 3.3v - 1.5v = +1.8v or 0.6v above the default v cm voltage. using these default conditions , and the maximum positive excursion of 0.6v above the 1.2v output v cm setting, the maximum differential v p-p swing will be 4x this 0.6v single-ended limit or 2.4v p-p . where +vs is increased, the limit then becomes the 0.9v below v cm , but then the absolute maximum differential v p-p is then 4 x 0.9v to 3.6v p-p . so for instance, to get this maximum output swing, increase the supply voltage until +vs - 1.5v > v cm + 0.9v. if we assume a v cm voltage of 1.3v for instance, then 1.3v + 0.9v + 1.5v = 3.7v will give an unclipped 3.6v p-p output capability. the v p-p reported in figure 27 is an asymmetrically clipped maximum swing. going 10% above this 3.7v target to 4.1v will be within the recommended operating range and give some tolerancing headroom that would also suggest the v cm voltage be moved up to approximately 1.5v, which coincides with the default output v cm from figure 27. operating at +4.1v single supply in a figure 29 type configuration will give the maximum linear differential output swing of 3.6v p-p . the differential inputs internal to the ISL55211 also have operating range limits relative to the supply voltages. operating in an ac-coupled circuit like figure 29 will produce an input common mode voltage equal to the outputs. the inputs can operate with full linearity with this v cm voltage down to 1.1v above the -vs supply. on the default 1.2v output v cm on +3.3v supplies this gives a 100mv guardband on the input v cm voltages. overriding the default v cm by applying a control voltage to the v cm pin should be done with care in going towards the negative supply due to this limit. on the + side, the maximum input v cm above the -vs supply is 2v so there is more room to move the output v cm up than down from the default value. power supply, shutdown, and thermal considerations the ISL55211 is intended for single supply operation from 3.0v to 4.2v with an absolute maximum setting of 4.5v. the 3.3v supply current is trimmed to be nominally 35ma at +25c ambient. figure 28 shows the supply current for nominal +25c and -40c to +85c operation over the specified maximum supply range. the input stage is biased from an internal voltage reference from the negative supp ly giving the exceptional 90db low frequency psrr shown in figure 26. since the input stage bias is from a re-regulated internal supply, a simple approach to single +5v operation can be supported as shown in figure 33. here, a simple ir drop from the +5v supply will bring the operating supply voltage for the ISL55211 into its allowed range. figure 33 shows example calculations for the voltage range at the ISL55211 +vs pin assuming a 5% tolerance on the +5v supply and a 35ma to 55ma range on the total supply current. considerin g the 34ma to 44ma quiescent current range from figure 28 over the -40c to +85c ambient, and the 3.4v to 4.4v supply voltage range assumed here, this is designing for a 1ma to 11ma average load current, which should be adequate for most intended application loads. good supply decoupling at the device pins is required for this simple solution to still provide exceptional hd performance.
ISL55211 14 fn7868.0 june 21, 2011 the ISL55211 includes a power shutdown feature that can be used to reduce system power dissipation when signal path operation is not required. this pin (pd ) is referenced to -vs and must be asserted low to activate the shutdown feature. when not used, a 10k ? external resistor to +vs should be used to assert a high level at this pin. digital control on this pin can be either an open collector output (using that 10k ? pull-up) or a cmos logic line running off the same +vs as the amplifier. for split supply operation, the pd pins must be pulled to below -vs + 0.54v to disable. since the ISL55211 operates as a differential inverting op amp, there is only modest signal path isolation when disabled, as shown in figure 24. the inputs include 2 pairs of back to back low capacitance diodes intended to protect any subsequent devices from large input signals during shutdown. those diodes limit the maximum overdrive voltage across th e input to approximately 1.0v in each polarity. the internal r g resistors of test circuit 1 limit the current into those diodes under this condition. the supply current in shutdown does not reduce to zero as internal circuitry is still active to hold the output common mode voltage at the v cm voltage even during shutdown. this is intended to hold the ISL55211 outputs near the desire d common mode output level during shutdown. this improves the turn on characteristic and keeps those output voltages in a safe range for downstream circuitry. the very low internal power dissipation of the ISL55211, along with the excellent thermal conductivity of the tqfn package when the exposed metal pad is tied to a conductive plate, reduces the t j rise above ambient to very modest levels. assuming a nominal 115mw dissipation and using the 63c/w measured thermal impedance from junction to ambient, gives a rise of only 0.115*63 = 7.2c. operation at elevated ambient temperatures is easily supported given this very low internal rise to junction. the maximum internal junction temperatures would occur at maximum supply voltage, +85c maximum ambient operating, and where the tqfn exposed pad is not tied to a conductive layer. where the tqfn must be mounted with an insulating layer to the exposed metal plate, such as in a split supply application, device measurements show an increased thermal impedance junction to ambient of +120c/w. using this, and a maximum quiescent internal power on 4.5v absolute maximum, which shows 45ma for +85c maximum operating ambient from figure 27, we get 4.5v*45ma*+120c/w = +24c rise above +85c or approximately +109c operating t j maximum - still well below the specified absolute maximum operating junction temperature of +135c. noise analysis the decompensated voltage feedback design of the ISL55211 provides very low input voltage and current noise. based on the isl55210, these internal noise terms are 0.85nv/ hz differential voltage noise and a 5pa/ hz current noise term on each side. since the ISL55211 is an internally fixed gain version, these internal noise terms will produce only a few set of output noise values. figure 34 shows the analysis model for just the ISL55211 with no input transformer while table 3 shows the resulting output and input referred differential spot noise voltages using equation 1. with equal feedback and gain resistors, the total output noise expression becomes very simple. this is shown as equation 1. the ng term in this equation is the noise gain = 1 + r f /r g . the last term in equation 1 captures both the r f and r g resistor noise terms. table 3 evaluates this expression for the 3 possible internal gains with a fixed 500 ? internal feedback. nv/ hz figure 33. operating from a single +5v supply c in 1:n ISL55211 +5v 5% + - v i v cm v o r f r f r g r g 10k pd r o r o 24.3 35 55ma 3.4 4.4v 10nf 2.2f + table 3. output and input spot noise from equation 1 for the 3 gains of the ISL55211 r g ( ) gain v/v noise gain v/v input referred e o nv/ hz e ni nv/ hz 250 2 3 8.19 4.09 125 4 5 10.51 2.63 100 5 6 11.60 2.32 figure 34. amplifier only noise model ISL55211 + - e o r f r f r g r g * i n 4ktr g * i n * 4ktr f 4ktr f * * e n 500 500 4ktr g (eq. 1) e 0 e n ? ng () 2 2i n r f () 2 24ktr f ng () ++
ISL55211 15 fn7868.0 june 21, 2011 adding an input transformer can improve the input referred noise by adding a noiseless voltage gain. starting from test circuit 1 of figure 29, and assuming the source shows a matched broadband source r s that will be matched by the input referred parallel combination of 2*r g ||r t , a noise gain analysis circuit can be developed as shown in figure 35. stepping through the 3 gain settings with two input transformers will allow the noise gain to be calculated for the circuit of figure 35, which is all that is needed in equation 1 to arrive at an output differential noise (since r f is fixed at 500 ? ). doing this gives table 4. the signal gain is taken from the input of the transformer for this analysis and shows the total in put referred noise going below 0.9nv at the highest gain setting here. while this analysis is including the approximate 0.9nv noise of a 50 ? source r, that noise is assumed to be divided down by 2 to the input of the transformer, which explains the total input referred noise showing up as less than just a 50 ? resistor. the total output differential noise goes below 9nv/ hz at the higher gains settings using this input transformer technique. for even lower noise, consider the isl55210 where the input r t element is generally not required. in th at case, simply setting r g to the desired input z and adjusting r f to the desired gain will give an output noise that is slightly lo wer than shown previously for the same input transformer due to the removal of the r t element. driving cap and filter loads most applications will drive a resistive or filter load. the ISL55211 is robust to direct capaci tive load on the outputs up to approximately 10pf. for frequency re sponse flatness, it is best to avoid any output pin capacitance as much as possible - as the capacitance increases, the high frequency portion of the ISL55211 (>1ghz) response will start to show considerable peaking. no oscillations were observed up through 10pf load on each output. for ac-coupled applications, an output network that is a small series resistor (10 to 50 ? ) into a blocking capacitor is preferred. this series resistor will isolat e parasitic capacitance to ground from the internally closed loop output stage of the amplifier and de-que the self resonance of the blocking capacitors. once the output stage sees this resistive element first, the remaining part of a passive filter design can be done without fear of amplifier instability. driving adc's many of the intended applications for the ISL55211 are as a low power, very high dynamic range, last stage interface to high performance adc's. the lowest power adc's, such as the isla214p50 shown on the front page, include an innovative "femto-charge?" internal architec ture that eliminates op amps from the adc design and only passe s signal charge from stage to stage. this greatly reduces the required quiescent power for these adc's but then that signal ch arge has to be provided by the external circuit at the two input pi ns. this appears on an adc like the isla112p50 as a clock rate dependent common mode input current that must be supplied by the interface circuit. at 500mhz, this dc current is 1.3m a on each input for the 14-bit isla214p50. most interfaces will also include an interstage noise power bandlimiting filter between the am plifier and the adc. this filter needs to be designed considering the loading of the amplifier, any v cm level shifting that needs to take place, the filter shape, and this icm issue into the adc input pins. here are 4 example topologies suitable for different situations. 1. ac-coupled, broadband rlc interstage filter design. this approach lets the amplifier op erate at its desired output common mode, then provides the adc common mode voltage and current through a bias path as part of the filters designs last stage r values. the v b is set to include the ir loss from that voltage to the adc inputs due to the i cm current. table 4. output noise and input referred equivalent noise for the transformer coupled input ISL55211 intended transformer + internal gain settings noise gain v/v input referred input xfmr turns ratio internal r g value ( ) gain (v/v) v o /v i gain (db) v o /v i external r t value ( ) total gain resistor for ng ( ) e o nv/ hz e ni nv/ hz 1:1.4 250 2.8 9 122 277.48 2.80 7.94 2.834811 1:1.4 125 5.6 15 162 155.92 4.21 9.62 1.718338 1:1.4 100 7 17 192 132.88 4.76 10.25 1.46452 1:2 250 4 12 333 312.48 2.60 7.68 1.920066 1:2 125 8 18 1020 208.61 3.40 8.67 1.083876 1:2 100 10 20 100 8 200.00 3.50 8.79 0.879492 figure 35. noise gain model for the transformer coupled input circuit of figure 29 ISL55211 + - r f r f r g r g 500 n 2 r s /2 r t /2 n 2 r s /2 r t /2 500
ISL55211 16 fn7868.0 june 21, 2011 2. ac-coupled, higher frequency range interstage filter design. this design replaces the r t resistors in figure 35 with large valued inductors and implements the filter just using shunt resistors at the end of the rlc filter. in this case, the adc v cm can be tied to the centerpoint of the bias path inductors (very much like a bias-t) to provid e the common mode voltage and current to the adc inputs. these bias inductors do limit the low frequency end of the operat ion where, with 1h values, operation from 10mhz to 200mhz is supported using the approach of figure 37. 3. ac-coupled with output side transformer. this design includes an output side transformer, very similar to adc characterization circuits. this a pproach allows a slightly lower amplifier output swing (if n>1 is used) and very easy 2nd or 3rd order low pass responses to be implemented. it also provides the i cm and v cm bias to the adc through the transformer centertap. this approach would be attractive for higher adc input swing target s and more aggressive noise power bandwidth control needs. figure 1 on page 1 is an example showing this approach. 4. dc-coupled with adc v cm and i cm provided from the amplifier. here, dc to very high frequency interstage low pass filter can be provided. again, the r s element must be low to reduce the ir drop from the v cm of the converter, which now shows up on the output of the ISL55211, to the adc input pins. figure 36. ac- coupled broadband rlc interstage filter design r t r t i cm i cm c t c t r in c in adc s t r r > l s l s v b 2 cm t cm b v r i v = ? in+ in- ISL55211 v cm 1 r s r s +3.3v 1.2v c b c b v cm2 figure 37. ac-coupled, higher frequency rlc interstage filter design r t c t c t r in c in a d c in + in - l s l s l p l p i sl55211 v cm 1 r s r s +3. 3v 1.2v c b c b i cm i cm v cm2 s l l p >> figure 38. ac-coupled with output side transformer 2i cm ISL55211 v c m 1 r s r s +3. 3v 1.2v c b c b r t r t i c m i c m c t c t r in c in a dc v cm2 in + in - 1:n r t < 30 figure 39. dc-coupled with a v cm voltage from the adc 30 s r r t i cm i cm c t c t r in c in adc v cm2 l s l s in+ in- ISL55211 v cm r s r s +3.3v
ISL55211 17 fn7868.0 june 21, 2011 layout considerations the ISL55211 pinout is organized to isolate signal i/o along one axis of the package with ground, power and control pins on the other axis. ground and power should be planes coming into the upper and lower sides of the package (see ?pin configuration? on page 2). the signal i/o should be laid out as tight as possible. the ground pins and package backside metal contact should be connected into a good ground plane. the power supply should have both a large values electrolytic cap to ground, then a high frequency ferrite beads, then 0.01f smd ceramic caps at the supply pins. some improvement in hd2 performance may be experienced by placing and x2y cap between the two vs+ pins and ground underneath the package on the board back side. this is 3 terminal device that is in cluded in the evaluation board layout. evaluation board (rev. c) test circuit 1 (figure 29) is impl emented on an evaluation board available from intersil. this boar d includes a numb er of optional features that not populated as the board is delivered. the full evaluation circuit is shown in figure 40 where unloaded (optional) elements are shown in green. the nominal supply voltage for the board and device is a single 3.3v supply. from this, the isl55210, ISL55211 generates an internal common mode voltage of approximately 1.2v. that voltage can be overridden by populating the two resistors and potentiometer shown as r 19 to r 21 above. the primary test purpose for this board is to implement different interstage differential passive filters intended for the adc interface along with the adc input impedances. the board is delivered with only the output r's loaded to give a 200 differential load. this is done using the two 85 resistors as r9 and r 10 , then the 4 0 elements (r 10 , r 12 , r 24 , and r 25 ) and finally the two shunt elements r 13 and r 14 set to 35.5 . including the 50 measurement load on the output side of the 1:1 transformer reflecting in parallel with the two 35 ? resistors takes the nominal ac shunt impedance to 71 ||50 = 29.3 . this adds to the two 85 series output elements to give a total load across the amplifier outputs of 170 + 29.3 = 199.3 . to test a particular adc interface rlc filter and converter input impedance, replace r 11 and r 12 with rf chip inductors, load c 10 and c 11 with the specified adc input capacitance and r 26 with the specified adc differenti al input r. with these loaded, the remaining resistive elements (r 24 , r 25 , r 13 , r 14 ) are set to hit a desired total parallel impedance to implement the desired filter (must be < than the adc inpu t differential r since that sits in parallel with any "external" elements) and achieve a 250 source looking into each side of the tap point transformer. this evaluation board includes a user's manual showing a number of example circuits and te sted results and is available on the intersil web site on the is l55211 product information page.
ISL55211 18 fn7868.0 june 21, 2011 in out c2 100nf c4 100nf c5 100nf r3 0ohm r4 0ohm adt2-1t r6 0ohm c3 100nf r7 0ohm r5 dnp r8 dnp r15 50ohm r9 85ohm c6 1uf c7 1uf r10 85ohm fb+ 1 vi- 2 vi+ 3 fb- 4 gnd 5 vs+ 6 pd 7 gnd 8 vo- 9 nc 10 nc 11 vo+ 12 gnd 13 vcm 14 vs+ 15 gnd 16 u1 isl55210/11 adt1-1wt r0 162ohm r16 50ohm c8 1uf r11 0ohm r12 0ohm r13 35.5ohm r14 35.5ohm r17 200ohm r20 200ohm/dnp r18 50ohm r21 200ohm/dnp c9 100nf r19 1k/dnp tp1 test point tp2 difprobe r22 50ohm pd c1 1uf r2 dnp r1 dnp +vs gnd + c1001 4.7uf l1 bead c1002 1.0uf vcc r23 0ohm r24 0ohm r25 0ohm r26 dnp c11 dnp c10 dnp r27 0ohm r28 0ohm/dnp nc 1 a 2 gnd 3 y 4 vcc 5 74ahc1g04 cterm1 2.2pf cterm2 2.2pf r1007 0ohm/dnp r1006 0ohm/dnp r1009 0ohm/dnp r1008 0ohm/dnp r1010 0ohm/dnp r1002 0ohm/dnp r1001 0ohm/dnp r1004 0ohm/dnp r1003 0ohm/dnp r1005 0ohm/dnp r1011 0ohm/dnp figure 40. isl55210, ISL55211 single input transformer evaluation board rev c
ISL55211 19 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7868.0 june 21, 2011 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentation an d related parts, please see the respective device information page on intersil.com: ISL55211 to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff fits are available from our website at: http://rel.intersil.co m/reports/search.php revision history the revision history provided is for inform ational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change june 21, 2011 fn7868.0 initial release
ISL55211 20 fn7868.0 june 21, 2011 package outline drawing l16.3x3d 16 lead thin quad flat no-lead plastic package rev 0, 3/10 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.15mm and 0.25mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to asme y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view (4x) 0.15 index area pin 1 a 3.00 b 3.00 pin #1 b 0.10 m a c 4 6 6 0.05 1 12 4 9 13 16 8 5 1.60 sq 16x 0.23 16x 0.400.10 4x 1.50 12x 0.50 (16x 0.60) ( 1.60) (2.80 typ) (16x 0.23) (12x 0.50) c 0 . 2 ref 0 . 05 max. 0 . 02 nom. 5 0.75 0.05 0.08 0.10 c c c index area see detail ?x? jedec reference draw ing: mo-220 weed. 7.

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